Rick Huang

产品市场经理，爱普科技（AP Memory）

Abstract

优化系统功耗的重要性可谓不言而喻。作为SoC生态系统的一部分，存储子系统对系统整体性能有重要影响，同时，对于控制系统的功耗也非常关键。在过去的20年里，AP Memory核心团队一直致力于提供创新的存储解决方案。

AP Memory推出了最具成本效益、低引脚数、超低功耗的PSRAM存储解决方案。如今，日益增长的物联网和可穿戴设备需要大量计算能力和存储带宽，同时对低功耗、低引脚数、小体积和高性能的需求也未降低。AP Memory创新的物联网RAMs成为多种应用的选择，包括可穿戴设备、人工智能边缘设备、智能家居、智能工厂和蜂窝物联网等。领先的SoC制造商和IP供应商均支持AP Memory的物联网RAM接口。

在本次演讲中，您将了解AP Memory最新的以客户为中心的PSRAM存储产品系列和关键性能矩阵，为您的应用选择最合适的功效优化解决方案。

Osvaldo Martinello

Foundation IP 业务高级研发总监，Silvaco, Inc.

Abstract

与MOSFET相比，FinFET技术在提高设计集成度和性能的同时，也能降低功耗，然而，FinFET的设计复杂性更高，不仅需要更高质量的版图，而且设计规则也更加复杂，也更难修正DRC的错误。在本次演讲中，我们将回顾FinFET标准单元布局设计中最具挑战性的问题，以及如何用Silvaco Cello解决这些问题。

Jeff Elias

IP业务总经理及公司副总裁，Silvaco, Inc.

Abstract

介绍Silvaco Design IP业务的进展及未来发展方向，包括近期推出的新产品、收购情况和合作伙伴关系等。

赵梓夷 Ziyi Zhao

高级应用工程师，Silvaco中国

Abstract

物理验证在芯片设计领域具有非常重要的地位，Silvaco近期推出了新型工具SmartDRC/LVS，用于模拟、数字和数模混合等IC设计流程中的物理验证，如设计规则检查（DRC）以及电路图版图对比校验（LVS）。SmartDRC/LVS拥有Silvaco独特的运算体系，能够高效并行调用多核CPU进行计算，精准处理复杂图形，为客户提供卓越的产品体验和可视化纠察方案。SmartDRC/LVS开发的物理验证文件已被流片验证，并通过了多家半导体制造工厂的认证，如Tower Semiconductor、X-FAB和UMC。 SmartDRC/LVS已经嵌入Silvaco版图编辑软件Expert和电路编辑软件Gateway。通过集成相关流程软件，可以帮助客户可视化地查明设计缺陷与版图错误，帮助客户快速解决问题；也可用于抽取版图网表，为客户提供版图与电路图对比校验的解决方案。

Jean Pierre Raskin

鲁汶大学教授

Abstract

精准的寄生参数模型对高频下的IC 设计非常重要，其中衬底更是有不可忽视的作用。由于半导体材料电阻率在小信号下具有强烈的各向异性，在大信号激发下各向异性更加显著，对衬底的建模如今仍是一项挑战。

Silvaco 器件仿真工具可对各种类型硅基衬底的小信号和大信号表现建模，开发的模型严格遵循了半导体材料的物理原则，考虑了电荷平衡相互作用，能揭示在准静态和强非平衡瞬态条件下各种硅基衬底的内部工作原理。

Silvaco开发出的大信号建模方案已被证明非常稳定，即在空间和时间上收敛，并且经二十多种不同硅基衬底的大量测量数据验证。

Rick Huang

AP Memory

Abstract

The drive for power efficient system solution is everywhere. As a part of the SoC ecosystem, Memory subsystem is one of the key components to boost overall system performance while keeping the system power under control. AP Memory core team has been involved in providing innovative memory solution for past 20 years.

AP Memory develops the most cost effective, low pin count, ultra-low power PSRAM memory solutions. Many IOT and Wearable applications today demand for a lot of computing power and memory bandwidth without any compromise on low power, low pin count and space constraints and performance competitiveness requirements. APM's Innovative IOT RAMs become a natural choice for several applications such as wearables, edge AI, smart home, smart factory, cellular IOT and many more. Leading edge SoC maker and IP providers are supporting AP Memory's IoT RAM interfaces.

During this session you will learn more about our latest customer centric PSRAM memory families and key performance matrix to choose the most suitable power optimized memory solution for your application.

常志强 Kevin Chang

TCAD 技术支持部经理，Silvaco中国

Abstract

介绍Silvaco全新的Domain Decompostion算法在提取寄生参数方面的应用

李栋良 Dongliang Li

资深TCAD工程师，Silvaco中国

Abstract

以行业头部客户的案例为基础，介绍 Silvaco TCAD 在显示面板领域的最新应用

Bogdan Tudor

高级经理，Silvaco, Inc.

Abstract

介绍Utmost IV 的核心优势，分享产品在显示面板行业的应用案例，并基于2021 年Baseline，介绍升级后的产品功能、全新的Corner模块和 Utmost IV Retargeting模块。Silvaco建模服务通过SPICE建模的专业知识，可帮助显示面板行业的客户准确提取模型，为器件建模加速。

Sripriya Raghavendran – Silvaco, Inc.

应用工程师, Silvaco Inc

Abstract

介绍最新推出的Device Explorer及其使用方法。我们将展示它如何帮助设计人员更好了解PDK中的器件特性，以便设计者在快速准确地找到适合的器件，在设计之初就可以对电路进行优化。它拥有Silvaco独一无二的技术，可帮助用户更快速地优化电路设计。

赵梓夷 Ziyi Zhao

高级应用工程师，Silvaco中国

Abstract

介绍Silvaco物理验证新工具SmartDRC/LVS，分享其在显示面板领域的应用。

Won-Seok Lee

高级应用工程师，Silvaco韩国

Abstract

AMOLED技术存在一些众所周知的问题，例如由于TFT器件磁滞特性而导致的图像粘滞。作为LTPS背板成熟的器件，TFT器件引入的残留图像会导致面板质量问题。磁滞问题是众所周知的技术问题，并且目前尚未找到解决方法，因此，面板企业必须在生产过程中尽量最小化和补偿这些问题带来的影响。为了抑制磁滞行为，需要使用动态VTO转变、SS摆动甚至具有磁滞模型的迁移率，而不是使用静态模型，来正确重现TFT器件的工作特性。Silvaco成功开发了磁滞模型，可用测试实验数据进行定制和建模，基于此模型，可以找到一种最佳方案来抑制磁滞问题，从而获得高质量、高性能的面板。

Dr. Alex Samoylov

EM/IR 分析高级经理，Silvaco

Abstract

Silvaco近期推出了令人兴奋的新产品SiCure，用于分析IR-drop和EM。SiCure使用简单，对输入数据要求很低，而且结果非常准确，能够更快发现版图设计中的问题，从而提高投片的成功率。本次演讲将介绍完整的分析流程，以及在设计规模较大的电路时，对典型问题的解决办法。

Dan Jiang

Application Engineer, Silvaco China, Ltd

Abstract

VarMan is not only an innovation, is Statistical sampling was used and real and effective simulation, and a breakthrough with a new methodology for addressing and analyzing process variation in design. While the High Sigma Analysis is a very powerful tool dedicated to detection of failures with high accuracy and thus obtaining higher quality, the Fast Monte Carlo is powerful and flexible by helping to manage quality and provide higher levels of productivity and design confidence. Using VarMan, the designer doesn’t need to be a statistician or a “stochastic designer” - he or she will always be the designer and decision-maker.

Ke Liu

Application Engineer Manager, Silvaco China, Ltd

Abstract

Foundation IP reuse for different technologies, cell architectures, applications. For example, the high density, Low power and High performance. Layout engineers have to edit every single layout (imagine an 800-cell library), adjust sizes and fix DRCs for the target technology. This manual layout development requires detailed, repetitive work with polygons to create DRC clean cells. Reuse gain is practically zero. Better alternative: use Cello to automatically adjust geometry sizes and fix design rules. Meanwhile. Cello can support the layout optimization and adapt layout to technology process changes. So Months of manual labor become hours of runtime.

Kevin Chang

TCAD Application Engineer Manager, Silvaco China Co. Ltd

Abstract

Introduce the solution of Silvaco tools on MicroLED simulation and application, this presentation will cover the flow from the structure generation to the physical model, numerical results analysis, and device characteristics, focus on the new features from Silvaco for the MicroLED simulation.

Dr. Bogdan Tudor

Senior Corporate Application Engineer, Silvaco Inc

Abstract

Brief review of the Silvaco Modeling capabilities. Introducing the Quick-start Templates for TFT Device Modeling. Reviewing Modeling Solutions for OLED.

Takeshi Kuwagagi

APAC FAE manager, Silvaco Japan

Abstract

Clever, advanced 3D/phisical-based parasitic extractor fills several requirements for FPD pixcel design, such as very high accuracy, ease-of-use by its execution dashboard, and robustness with complex non-planer interconnect structure. In this presentation, we will discuss what is required for FPD pixel design, and why Clever is the best fit on this purpose.

Babak Taheri

CEO/CTO, Silvaco Inc

Abstract

Babak Taheri, CEO/CTO of Silvaco provides an update on Silvaco products development and a perspective on major trends and challenges facing semiconductor businesses, including dealing with the COVID-19 crisis, what we have learned, and how the new situation affects the market. Different segments including Automotive, IoT, Memory, 5G networks, Security will be covered.

Rahul Goyal

Vice President and Director of R&D Strategic Enablement, Intel

Abstract

Rahul Goyal will present on the latest industry trends and challenges for creating advanced semiconductors for computing used in a wide range of end markets, including servers, mobile, AI/ML, automotive, and 5G applications. He will address key challenges for Intel in pursuit of heterogeneous integration and Intel’s pillars of technology. He will cover how Intel design community looks to EDA suppliers for TCAD, IP and design analysis and what challenges they see coming in future designs.

Richard Trihy

Vice President of Engineering, Design Enablement, GLOBALFOUNDRIES

Abstract

Mr. Trihy will present trends and challenges for the semiconductor industry from a foundry perspective, and how GLOBALFOUNDRIES’ technology solutions meet the needs of fabless companies to develop innovative products for high-growth market segments. These solutions include GF’s differentiated 22FDX® (22nm FD-SOI) platform and GF’s 12LP finfet and 12LP+ platforms and a full breadth of technologies to support 5G mmWave, edge AI, Internet of Things (IoT), automotive, satellite communications, security, and other applications. He will cover how GF partners with EDA and IP partners like Silvaco for design IP, EDA software, and development of process design kits (PDKs) to meet the dynamic needs of clients across the globe.

GLOBALFOUNDRIES (GF) is the world’s leading specialty foundry. GF delivers differentiated feature-rich solutions that enable its clients to develop innovative products for high-growth market segments. GF provides a broad range of platforms and features with a unique mix of design, development, and fabrication services. With an at-scale manufacturing footprint spanning the U.S., Europe and Asia, GF has the flexibility and agility to meet the dynamic needs of clients across the globe. GF is owned by Mubadala Investment Company.

Gurtej S. Sandhu

Senior Fellow and Vice President, Micron Technology

Abstract

TBD

Babak Taheri

CEO, Silvaco Inc

Abstract

Lorem Ipsum is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry’s standard dummy text ever since the 1500s, when an unknown printer took a galley of type and scrambled it to make a type specimen book. It has survived not only five centuries, but also the leap into electronic typesetting, remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset sheets containing Lorem Ipsum passages, and more recently with desktop publishing software like Aldus PageMaker including versions of Lorem Ipsum.

Stefano Pettazzi

Senior Applications Engineer. Silvaco, Inc.

Abstract

Designers of Flat Panel Displays and Detectors often rely on a variety of point tools from different EDA vendors that make the design flow discontinuous and difficult to integrate. These challenges together with specific advanced display technology requirements are addressed by the seamless and unique Silvaco TCAD-EDA flow. This presentation highlights how leading displays and detectors companies exploit the capabilities of Silvaco tools for schematic and layout editing, very accurate field solver-based parasitic extraction required by modern TFT technology, back-annotation of parasitic RC elements into the netlist and fast and accurate spice simulations of large arrays of pixels.

Jin Jang

Director of the Advanced Display Research Center, Kyung Hee Univeristy

Abstract

Foldable and rollable displays are of increasing interest recently. I will discuss the key technologies of TFTs for those applications. Non-laser detach technology was developed by using a CNTGO buffer layer inserted on carrier glass and then PI substrate coated. A CNT/GO buffer layer helps easy detach and more self-standing of plastic substrate [1]. We made oxide and LTPS TFTs on PI substrate using CNTGO buffer layer and investigated the effect of bending and folding on the electrical properties of TFTs. Tensile stress is found to give more change to the TFT performance for both LTPS and oxide TFTs compared to compressive stress [2]. These results are related with out-folding or in-folding of smartphone displays. The split of both source/drain and semiconductor layer is important for more foldable TFTs [3]. The device performance is also improved a lot by splitting active-layer for oxide TFTs [4]. The TFT in neutral plane is also very robust under bending [5]. I will discuss the strain effect on TFTs with out-folding or in-folding. The effect of grain boundaries on the foldability will be also touched [6-7].

Jeong-Ik Lee

Assistant Vice President Reality Devices Research Division, ETRI

Abstract

Flexible electronics has grown as a main stream research field for the potential application to wearable/healthcare monitoring, smart packaging as well as flexible displays. To accelerate technology development and expand the development eco-system of flexible electronics, it is important to establish a R&D platform for flexible electronics. ETRI(Electronics & Telecommunications Research Institute) has worked on flexible displays and accumulated lots of research experience for flexible electronics including conductive metal lines, TFT circuits, and OLEDs on flexible films. By using those experience and the collaboration with SILVACO, we have tried to establish the flexible electronics R&D platform (FERP) and some of efforts have been presented at the last year SURGE. We have checked the status of the FERP by fabricating some flexible electronic devices according to the demand of the external researchers. Based on those results, the progress and current status of the FERP in ETRI will be presented.

仲島 義晴様

株式会社ジャパンディスプレイ 執行役員 CTO 兼 R&D本部長

概要

ジャパンディスプレイの手掛けるディスプレイのコア技術及び最新技術を解説する。また、ディスプレイ技術の応用として考えられる各種センサ技術について紹介する。

吉崎 昇一様

シリコンライブラリ株式会社 取締役

概要

シリコンライブラリ株式会社は、高速インターフェースのIP開発・販売を主事業としています。なかでもシリアル信号の送受信を担う物理層（PHY）の設計においては、伝送速度の上昇やプロセスの微細化にともない、アナログ特性の検証に費やすシミュレーション時間の増加が課題になっています。本講演では、Jivavo Proによるネットリストリダクションを用いたシミュレーションの実例を紹介します。

右田 学様

協栄産業株式会社 R&D事業部/IC開発第二部/部長

概要

協栄産業にてシルバコ設計ツールを活用及び他ベンダーツールと併用した設計方法を、回路・レイアウト設計に対しご紹介。

John Kent

Executive Vice President, Technology Development and Design Enablement, SkyWater Technology

Abstract

Technology diversity is rapidly increasing across industries and along with it, demand for innovation. These dynamics are pushing the limits of existing technology development and production paradigms. This growing demand for innovation requires new engagement models and service architectures to enable more people to participate in the innovation process. This will require methods to enable a broader range of disciplines to produce hardware and design methodologies that improve time to product and product to market timelines. By lowering these barriers we can together harness the long tail of innovation and unleash an incredibly powerful innovation engine for post-Moore's law reality we are living in.

Thomas Blasei

VP & GM, EDA Division, Silvaco Inc

Abstract

Mr. Blaesi will give the update for the Analog Custom Design Flow and the direction of future development.

Alex Grudanov

Senior Director Advanced R&D, Silvaco Inc

Abstract

Physical Verification is the most critical stage of microchip design. In Analog IC-CAD Design Flow, SmartDRC/LVS is the new tool to perform physical verification of analog, digital and mixed-signal ICs including design rule checks (DRC), layout connectivity extraction and layout vs schematic (LVS) comparisons. Its unique architecture delivers high performance and capacity using multiple CPUs, accurate processing of complex shapes, and exceptional user productivity with fast interactive verification and intuitive debug. SmartDRC/LVS runsets are silicon-proven, and foundry certified for processes at Tower Semiconductor, X-FAB and UMC.

SmartDRC/LVS is tightly integrated with Silvaco’s Expert layout editor and Gateway schematic editor. The integration enables users to visualize and pinpoint design issues and design rule violations and quickly act to resolve them. SmartLVS extracts the netlist from layout and provides the user the ability to cross-compare the schematic and layout.

Dr. Alex Samoylov

Senior Manager, EM/IR Analysis, Silvaco Inc.

Abstract

Silvaco introduces exciting new development - tool for IR-drop and thermal analysis (EM is in roadmap). While being very accurate, tool is easy to use and input data requirements are minimal. Now it is easier than ever to find layout issues that will prevent successful tape-out. Complete analysis flow will be presented, and typical problems related to big design sizes will be addressed.

Scott Wedge

Senior R&D Engineer, Silvaco Inc

Abstract

A variety of circuit simulation approaches are useful in determining the steady-state behavior of oscillator and VCO circuits. SmartSpice transient analysis, with appropriate initial conditions, remains a valuable tool. The additional capabilities of steady-state harmonic balance and shooting Newton algorithms make possible very good predictions of oscillator waveforms, output spectrum, and frequency tunability. What has been more elusive and challenging for the designer is to have simulation results that give a practical understanding of how device noise will perturb their oscillators and create phase noise and jitter. In this presentation we discuss new capabilities available in SmartSpice RF to generate accurate impulse sensitivity functions (ISFs). These ISFs represent linear periodic time-varying descriptions of oscillator phase sensitivity to device noise and provide insights to the designer seeking the best noise performance possible.

Bogdan Tudor

Senior Manager, Head of Device Characterization, Silvaco Inc

Abstract

We examine some of the key advantages of Utmost IV and the major customer flows where Utmost IV is a key component. We present the 2021 Baseline main product enhancements. We also introduce the new Corner and Retargeting Utmost IV Module. To conclude, we provide a review of our modeling services through which we apply our SPICE modeling expertise to help our customers extract accurate models.

Sripriya Raghavendran

Applications Engineer, Silvaco Inc

Abstract

Abstract: Silvaco will present the newly released Device Explorer in a practical setting. We will show how designers can better understand which devices to use from their PDK and finding the right instance values quickly the first time, tuning your design while you create it. This unique and differentiating technology is only available from Silvaco and will allow users to create optimal circuits faster.

Dr. Firas Mohamed

VP Advanced R&D & GM Silvaco France

Abstract

Machine Learning is not new in EDA. Decades ago, ML or Deep Learning have been introduced but not explicitly mentioned. Recently, with the so-called and largely communicated revolution of Machine Learning, the EDA industry started looking for and/or disclosing their ML based solutions. This talk is a trial to tell a history of ML in EDA but also to present innovation and new approaches adopted and for which applications. The EDA specificity in term of computing resources, short project time, noisy data and variations at advanced nodes that forces the adaptation of the deployed ML methods to hard constraints. The talk will also present few samples of recent EDA tools ML-based with a focus on the 20 years ML works and developed solutions at Silvaco.

Jean-Baptiste Duluc

Senior Corporate Application Engineer, Silvaco Inc

Abstract

Due to Global and local process variation, combined with supply voltage and temperature variation, traditional approaches to performing 6-sigma and over verification becomes impractical due to the large number of simulations that are required.

Regarding the whole memory statistical analysis, this task becomes a challenge as the Full memory simulation at Spice level are impractical. Result using Fast Spice will also be biased by precision issues. One solution can be to perform statistical analysis on each individual block at different sigma corner and use convolution to achieve a result. But in fact, unrealistic results follow from this practice mainly due to complex statistic strategy to be defined.

The Silvaco VarMan XMA environment propose to have a well-defined workflow to carry out realistic full memory statistics. The presentation will describe the different steps achieving identification of worst PVT, of the most restrictive block with enough design feedback to drive the design optimization and detailed block analysis.

VarMan XMA, a working and efficient flow for Variation-aware memory design.

Vincent Annezo

Corporate Application Engineer, Silvaco Inc

Abstract

With each new semiconductor process node, process variation, both global and local, play an increasingly significant role in determining standard cell library performance. When combined with supply voltage and temperature variation, Standard cell characterization flows to finding 3-sigma process corners or performing 6-sigma verification requires intensive and long SPICE simulation runs on large compute farms.

To address this challenge, Silvaco has developed LibVar for use on digital libraries as an efficient and effective solution for variation-aware charaterisazion and verification.

Being non-intrusive and SPICE environment flexible, LibVar integrates easily into production environments.

For Standard cell, the LibVar technology is embedded in a cockpit that will drive to the most efficient analysis in term of speed and accuracy. Depending on the need, a dedicated algorithm will be applied.

From user point of view, a All In One integrated solution will be presented.

LibVar: low & high sigma efficient solution to boost digital library characterization and verification.

Simon-Alexis Abric

Corporate Application Engineer, Silvaco Inc

Abstract

Jivaro is a unique, stand-alone solution for the reduction of RLCK parasitic. It helps back-end SPICE users speed up post-layout simulation of huge extracted parasitic circuits, while keeping high accuracy of results. Jivaro offers a complete set of features to manage the reduction process while controlling accuracy. Out of the box, the operation of Jivaro is direct and simple, and the new automatic reduction setup meets the expectations of most designers.

On another hand, parasitic extraction is an important step in the physical back end verification flow and it is a cornerstone of sign off verification. On advanced technology nodes, the exponential growth of RC parasitics leads to even bigger problems when simulating or optimizing the layout. Yet parasitics are often seen as black box, leading to simulation results that are not what was expected. Our solution Viso allow to build a powerful QA methodology to prevent unexpected results from happening when the parasitic extraction flows are updated, but also help to understand what is inherently going-on in the post-layout design allowing to improve debugging and optimization steps.

Michael Uren

Research Professor in the Centre for Device Thermography and Reliability at the University of Bristol

Abstract

Gallium Nitride based devices are highly attractive for both RF and power switching applications due to a combination of outstanding materials properties. However although the basic principles are well understood and can now be accurately reproduced in device simulators, there are many important aspects that are still poorly understood and the subject of continuing active research. This talk will illustrate with some specific published examples how device simulation can be a powerful tool to help explain complex performance limiting device instabilities in both RF and power devices. In particular dynamic Ron in GaN-on-Si power switches, persistent photoconductivity in GaN HEMT epitaxy, and transconductance dispersion in iron doped GaN HEMTs.

Johannes Ender

Ph.D Student, Tu Vienna

Abstract

Spin-orbit torque magnetoresistive random access memory (SOT-MRAM) is a highly promising contender for replacing charge-based memories which currently dominate the fields of high-performance and high-density static RAM in registers and high-level caches. SOT-MRAM is non-volatile and exhibits ultra-fast operation and large endurance.

However, an unwanted external magnetic field is still required for deterministic switching of perpendicularly magnetized structures. A recently proposed SOT-MRAM cell architecture eliminates the need for this external magnetic field by sending current pulses through two orthogonal heavy metal lines attached to the magnetic free layer and is thus operated purely electrically. Finding and optimizing efficient pulse sequences for field-free switching remains a challenging problem. Reinforcement learning (RL) approaches have been shown to be efficient in finding solutions to this kind of complex problems. In RL an agent repeatedly interacts with an environment and learns to maximize its cumulative reward by adapting its policy of action.

We apply RL to determine optimal pulse sequences for fast switching of perpendicular SOTMRAM cells. Micromagnetic simulation serves as RL environment and is used to evaluate the performance of the learned pulse sequences. The results show that with the help of RL, pulse sequences can be found that lead to reliable switching even under variation of the current values and material parameters.

Dr. Eric Guichard

VP & GM, TCAD Division, Silvaco Inc

Abstract

Mr. Guichard will give the update for Silvaco TCAD simulation and the direction of future development.

Carlos Augusto, Ph.D.

Co-Founder and CTO, Quantum Semiconductor

Abstract

With the end of geometric scaling, semiconductor devices are increasingly adopting new materials to increase performance and functionality. Simulating mesoscopic-sized devices with new materials, about which there may be no reliable experimental characterization, requires both a quantum transport simulator such as Victory Atomistic, and Density Functional Theory (DFT) calculations of the fundamental optoelectronic properties of the new materials. The linking of DFT codes with Victory Atomistic is crucial for a complete TCAD workflow to explore leading edge CMOS, Lasers, Heterojunction Photo-Diodes, and more. Quantum Semiconductor LLC is working with Silvaco on the simulation of photo-absorption in direct band-gap Si-Ge-C superlattices. This talk will report on this collaboration with Silvaco.

Jean Pierre Raskin

Professor at Université catholique de Louvain

Abstract

At high frequency, the accurate modelling of parasitic elements is crucial to IC design. Substrate behaviour is a significant contributor to such parasitics, and its modelling is a challenge, not only under small-signal conditions due to strongly non-uniform resistivity profiles in semiconductor materials, but especially under large-amplitude excitations. In this work, Silvaco Device simulation tool is used to model both small- and large-signal behaviour of various types of silicon-based advanced substrates. The developed models are heavily based in material semiconductor physics, and the physical charge-balance interplay is rigorously studied, shedding light on the inner workings of a wide range of silicon-based substrates under both quasi-static and strong non-equilibrium transient conditions.

In particular, the developed large-signal modelling scheme is demonstrated to be stable, i.e. to converge in both space and time, and to correlate well to a wide set of measurement data from over 20 different silicon-based substrates.

Dr. Viktor Sverdlov

Director, Institute for Microelectronics, TU Wien

Abstract

Emerging spin-based nonvolatile magnetoresistive random access memories (MRAM) are electrically addressable, possess a simple structure, and offer endurance and speed superior to those of flash memory. To facilitate the development of emerging MRAM devices, we are devising a high performance finite element-method (FEM) based simulation approach. In particular, we are developing and implementing a three-dimensional self-consistent simulation tool to evaluate the spin accumulation, torques, and magnetization dynamics in magnetic structures including tunnel junctions. Efficient methods for calculating (i) the demagnetization field, (ii) coupled three-dimensional charge and spin transport trough a textured magnetic structure to evaluate (iii) spin-transfer torques driving (iv) the magnetization dynamics and switching are demonstrated.

Wolfgang Goes

Sr. Development Engineer, Silvaco, Inc.

Abstract

During the last years, the concept of resistive switching has attracted increasing industrial interest and new ReRAM technologies, such as Ag-GeSe3-Ni Conductive Bridge Random Access Memory (CBRAM), have emerged as promising candidates due to their low power consumption, high endurance, and fast switching times. To improve the understanding of these devices, TCAD simulations can be used to study the chemical processes behind the resistive switching. They allow identification of the key factors controlling the switching behavior and can significantly shorten the industrial development schedules. We will present a comprehensive but also flexible ReRAM model, based on our Chemistry Module in Silvaco’s device simulator Victory Device.

Dr. Tillmann Kubis

Katherine Ngai Pesic & Silvaco Research Assistant Professor of Electrical and Computer Engineering

Abstract

The nanodevice simulation tool NEMO5 has been developed at Purdue University since 2010 by more than 60 scientists and engineers. Code modularization, encapsulation, and polymorph code applicability were and are key elements that enabled the long-lasting success of the code. They frequently allowed for repurposing of validated and efficient numerical routines for applications they had not been designed for or that were even not imaginable at the time of their development. In this presentation, the NEMO5’s flexibility will be illustrated with quantum transport predictions of nanowire and cascade tunneling field effect transistors as well as with incoherent sca ttering in topological insulator surface states and with quantum computing applications. All presented features are fully supported by the commercial version of NEMO5, Victory Atomistic. Victory Atomistic users get full customization support for their specific application scenarios.

Stefania Carapezzi

Post Doc - Centre National de la Recherche Scientifique​

Abstract

The recent trend of development of the Internet of Things (IoT) technology calls for the implementation of Artificial Intelligence at the Edge. This imposes the devising of suitable computing engines overcoming the limitations of common von Neumann architectures. In this respect, oscillatory neural networks (ONNs) are appealing ultra-low-power neuromorphic architectures promising to perform sophisticated tasks, such as pattern recognition, in edge devices. Key elements of ONNs are the oscillators mimicking the neurons. The use of beyond-CMOS devices based on vanadium dioxide (VO2) to realize these oscillators is an innovative step for the ONN technology, compared to traditional realizations through CMOS-based oscillators. The core mechanism operating in VO2 devices is the insultor-to-metal transition (IMT) of VO2, which undergoes a phase transition triggered by the temperature induced by self-heating from a high-resistive monoclinic (M1) crystal structure to a low-resistive tetragonal rutile-like (R) one. The use of commercial TCAD software tools to simulate VO2 devices is essential prerequisite to boost the development of ONN technology. This requires in turn dedicated TCAD modeling approaches to simulate thermal-induced resistive switching effects in VO2 devices. In the present contribution, results will be shown over 3D electrothermal simulations of a relaxation oscillator based on a VO2 device and the impact of material properties and geometry over its self-oscillatory behavior will be investigated.

Dr. Munaf Rahimo

Founder and General Manager - mqSemi AG, Siwtzerland

Abstract

Silicon IGBT and SiC MOSFETs are today`s key power semiconductor switches for many power electronics converters such as those in automotive, renewables and industrial applications. Both device concepts continue to evolve and development trends are continuously targeting improved overall electrical and reliability performance at lower costs. In addition to established power device manufacturers, many start-up companies have been founded in recent years providing novel solutions. Many of these solutions are based on 3D design concepts to achieve higher performance levels. The proof of concept of such semiconductor designs at a practical level can be very costly for a new start-up company with limited funds. Therefore, to enable a faster and cost-effective track for the initial stages of value creation, 3D TCAD simulations for the proof of concept of such novel structures are required. For our start-up company mqSemi AG, a new S-MOS cell concept was introduced where Silvaco provided the necessary TCAD tools and support to demonstrate the concept functionality for 1200V Silicon IGBTs and SiC MOSFET. We will introduce mqSemi and the 3D TCAD models and simulation results while highlighting Silvaco`s powerful Victory Process and Design.

Jeff Elias

VP & GM, IP Division, Silvaco Inc

Abstract

Mr. Elias will give the update for Design IP and its direction for the future, including new product introductions, acquisitions and partnerships.

Michael Simmons

Technical Fellow, Wireless, Microchip Technology Inc.

Abstract

The drive to ultra-low power devices has historically focused on optimizing the Run/Active dynamic power and Sleep/Deep Sleep static power, through a variety of techniques, including smaller process geometries and coarse power domain management. This session from Microchip Technology will present practical lessons learned from a year-long quest to answer the question of “What’s Next ?”. It will cover a range of problems and techniques ranging from Foundation IP through SoC Architecture and Firmware across the entire product lifecycle from Fab to Field.

Kavya Prabha Divakarla

Automotive Systems Functional Safety Architect, NXP Semiconductors

Abstract

As the automotive industry is making a paradigm shift towards more Automated Vehicles, the evolution of Functional Safety concepts is becoming more evident. This session by NXP will focus on introducing the evolving Functional Safety trends in the automotive market in addition to describing how NXP tailors the ISO 26262 implementation of Functional Safety within the organization. A walkthrough of IP integration process into the SoC will also be provided.

Intel

Abstract

The Debug for I3C interface - Simplified Address-Mapped (SAM) debug add-on, is designed to allow for debug, trace, and perform test/failure analysis using an I3C peripheral. Using existing SCL and SDA pins of the I3C bus, it facilitates data transfer between the application and the peripheral that is being debugged. In this presentation, we discuss the details SAM debug add-on IP and connection to popular debug trace adapters such as ARM DAP, ARM-ETM/SWO, JTAG-TAP, RISC-V DMI/DM.

Alex de la Bastie

Business Development Director, AP Memory

Abstract

The drive for power efficient system solution is everywhere. As a part of the SoC ecosystem, Memory subsystem is one of the key components to boost overall system performance while keeping the system power under control. AP Memory core team has been involved in providing innovative memory solution for past 20 years.

AP Memory develops the most cost effective, low pin count, ultra-low power PSRAM memory solutions. Many IOT and Wearable applications today demand for a lot of computing power and memory bandwidth without any compromise on low power, low pin count and space constraints and performance competitiveness requirements. APM's Innovative IOT RAMs become a natural choice for several applications such as wearables, edge AI, smart home, smart factory, cellular IOT and many more. Leading edge SoC maker and IP providers are supporting AP Memory's IoT RAM interfaces.

During this session you will learn more about our latest customer centric PSRAM memory families and key performance matrix to choose the most suitable power optimized memory solution for your application.

Jonghoon Shin

Principal Engineer, Samsung Foundry

Abstract

Various attack techniques that violate the security and safety of SoC are developed day by day, and the techniques are becoming more sophisticated. For example, previous side channel analysis found out secret information by analyzing the correlation between security information and power consumption pattern or operation time difference, but recently, it has evolved to an analysis technique for cache hit/miss behavior or electromagnetic characteristics. In addition, it has also been combined with malware or fault injection method. Due to this trend, mobile, automotive and IoT products have to equip secure and cost-effective attack countermeasures and protection method, even if they are not security products such as Smart Card. In this presentation, you can find various kinds of attack to SoC product and Samsung Security IP/solution to prevent them in SoC.

Osvaldo Martinello

Senior R&D Director for the Foundation IP Group

Abstract

FinFET technologies have enabled designs with increased density and performance while reducing power, when compared to MOSFET. However, this comes at a cost of increased design complexity. Not only some undesirable layout dependent effects are more pronounced, but design rules have become more complex. Many design rules violations can no longer be fixed within a local scope, since they may span a large region of a standard-cell and involve several polygons. In this talk we are going to review some of the most challenging aspects of FinFET standard-cell layout design, and how Silvaco Cello can be used to address these issues.

Dr. Eric Guichard

VP & GM, TCAD Division, Silvaco Inc

Abstract

Mr. Guichard will give the update for Silvaco TCAD simulation and the direction of future development.

Yao-Wen Chang

Distinguished Professor & Dean, College of Electrical Engineering and Computer Science, National Taiwan University

Abstract

Critical technology drivers for advancing semiconductor technologies have created a world with massive information and data explosion, which drives the urgent needs of computing devices with higher performance, better power efficiency, and lower cost. To achieve the power, performance, and cost holy grail, we have two main directions for semiconductors: (1) More Moore with continued device scaling by using advanced technologies, and (2) More-than-Moore with 2.5D or 3D heterogeneous integration to pack diverse components into a system. In this talk, we investigate most expected More-Moore transistor, patterning, and interconnect technologies to push the limits of continued process scaling for better area, power, and performance, study More-than-Moore heterogeneous integration for better system-level power-performance-cost tradeoffs and higher design functionality, address their challenges for advanced circuit and system designs, highlight current EDA solutions, and identify research opportunities for the emerging challenges.

Yun-Li (Charles) Li, Ph.D

CEO, PlayNitride Inc.

Abstract

MicroLED display is an emerging technology with high brightness, high contrast, wide color gamut, best reliability, and high transparency.

In additional to traditional display applications, MicroLED display can be used for innovative display technology, such as transparent display, AR glasses, wearable devices, automotive display, ultra-large tiling display, and many new display scenarios.

PlayNitride is focusing on all MicroLED core technologies, including ultra-uniform wafer process, MicroLED chip process, mass transfer, mass inspection, and mass repair. Based on these proprietary technologies, PlayNitride has demonstrated 89-inch 5K ultrawide curved display by PixeLED Matrix solution, transparent / flexible / high HDR displays by PixeLED Display solution, and AR micro-display by μ-PixeLED solution.

MicroLED display can fulfill all display required features and will be a revolution of display industry.

Ya-Hsiang Tai

Professor, Department of Photonics, National Yang Ming Chiao Tung University

Abstract

Gap-type amorphous silicon (a-Si) thin-film transistor (TFT) can provide high photo current in simple device structure, which makes it suitable for large area sensing applications, especially for the optical fingerprint sensor in smart phones. The reason why the photo current is much higher when the device is operated in the on region than that in the off region is not well understood. In this study, we propose the mechanism to explain this special phenomenon for the gap-type a-Si TFT. Silvaco TCAD simulation is used to support the proposed mechanism, crosscheck the results of experiments, and investigate the factors of process development.

John Kent

Executive Vice President, Technology Development and Design Enablement, SkyWater Technology

Abstract

各行各业的技术都在发展变化，不断革新现有的技术和生产模式。日益增长的创新需求需要新的合作模式和服务架构，以支持更多人参与到创新过程中。面对这一趋势，硬件产品生产制造和进入市场的速度必须更快，因而我们需要寻找方法，让产品的设计和生产得到更多学科知识的支持。通过降低这些壁垒，利用创新的长尾，则可以在我们所处的后摩尔定律时代，打造出一个极其强大的创新引擎。

Eric Guichard博士

TCAD业务总经理及公司副总裁，Silvaco, Inc.

Abstract

Guichard博士将介绍Silvaco TCAD仿真工具的新功能，以及在未来的发展方向。

石立丽 Lili Shi

EDA高级应用工程师，Silvaco中国

Abstract

Jivaro 是一种独特的、独立的解决方案，应用于缩减 RLCK 的寄生参数,可以大幅提高后端 SPICE 用户对于大型寄生电路的后仿速度，并保证仿真结果的准确性。Jivaro 的操作简单直接，其最新的自动默认参数设置可满足大多数电路设计师的需求。

寄生参数提取是物理后端验证流程中的重要步骤，是最终设计数据验证的基石。在先进工艺节点中，RC 寄生参数的指数增长会对电路仿真或版图优化造成阻碍，然而，寄生效应像黑匣子一样无法直观地分析，容易导致仿真结果与预期不符。Viso可以构建强大的QA解决方案，避免在更新寄生参数提取流程时产生不符合预期的结果，帮助设计者了解版图的寄生参数数据，从而更精准的对电路设计进行优化

Dr. Munaf Rahimo

创始人兼总经理 ，mqSemi AG，Siwtzerland

Abstract

IGBT 和 SiC MOSFET半导体是当今许多开关电源（例如汽车、可再生能源和工业应用中的转换器）中的关键器件，其发展趋势一直是在更低的成本下实现更好的器件性能和更高的可靠性。除了老牌的功率器件制造商，近年来成立的许多提供创新解决方案的初创公司，其解决方案都基于3D设计来实现更高的性能。在实际产生中验证设计方案非常昂贵，对于资金有限的初创公司来说更是如，而3D TCAD仿真正能够快速且经济地进行芯片设计验证。

初创公司mqSemi AG借助Silvaco TCAD工具和支持，为1200V的IGBT 和 SiC MOSFET 设计了新的S-MOS功能概念 。在本次演讲中，我们将介绍mqSemi如何借助Silvaco 强大的Victory TCAD产品，实现3D TCAD器件建模和仿真设计

刘客 Ke Liu

技术支持经理，Silvaco中国

Abstract

对于新的半导体工艺节点，各种工艺偏差对标准单元库的性能都有很大影响。结合电压和温度的变化，为了获得标准单元3-sigma或6-sigma 的工艺特征值，往往需要在大型计算机集群上进行密集和长时间的 SPICE 仿真。

为了应对这一挑战，Silvaco 开发了一款应用于数字单元库的产品——LibVar，可以高效处理特征模型的差异并进行验证。LibVar可以轻松集成到SPICE环境中，也可嵌入引擎中对标准单元进行高速和准确的分析。LibVar可根据不同的需求调用不同的算法，能为客户提供一站式的集成解决方案。

LibVar为数字电路的特征模型和验证，以及低sigma和高 sigma 的分析，提供了高效的解决方案。

Ziyi Zhao

Silvaco Inc

Abstract

Physical Verification is the most critical stage of microchip design. In Analog IC-CAD Design Flow, SmartDRC/LVS is the new tool to perform physical verification of analog, digital and mixed-signal ICs including design rule checks (DRC), layout connectivity extraction and layout vs schematic (LVS) comparisons. Its unique architecture delivers high performance and capacity using multiple CPUs, accurate processing of complex shapes, and exceptional user productivity with fast interactive verification and intuitive debug. SmartDRC/LVS runsets are silicon-proven, and foundry certified for processes at Tower Semiconductor, X-FAB and UMC.

SmartDRC/LVS is tightly integrated with Silvaco’s Expert layout editor and Gateway schematic editor. The integration enables users to visualize and pinpoint design issues and design rule violations and quickly act to resolve them. SmartLVS extracts the netlist from layout and provides the user the ability to cross-compare the schematic and layout.

桑垣 武司

エンジニアリングマネージャ

概要

アナログ・カスタム・デザイン・フローの最新技術情報と今後のロードマップについてご紹介します

山本 順彦

Simulationシニア・アプリケーションエンジニア

概要

SmartSpiceの高速化とメモリ消費の低減についてご紹介します

伊藤 祐輔

ACDシニア・アプリケーションエンジニア

概要

IRドロップ、エレクトロマイグレーションそして熱などの問題を解決するための新しいソリューションをご紹介します。

秦野 泰治

ACDアプリケーションエンジニア

概要

CADチームと設計者の双方に有用な寄生RCLK リダクションツール Jivaro とその検証・解析ツール Alps の最新開発状況をご紹介します

樫村 薫

IPビジネスユニット　シニア・アプリケーションエンジニア

概要

デザインIPと今後の方向について、新製品と他社とのパートナーシップを交えながらご紹介します

分島 彰男様

名古屋工業大学 准教授

概要

GaNトランジスタは、移動体基地局増幅器半導体として、すでに商用化が進んでいる。一方で、トラップに起因した電流コラプスなどの現象といった基礎的検討も未だに並行して進められている状況である。本講演では、GaNトランジスタのトラップに起因した電流コラプスや発光現象といった基礎的検討から、今後普及が期待されているマイクロ波無線電力伝送への応用を概説するとともに、SILVACO・ATLASを用いたデバイス解析の併用について紹介する。

北村 元樹様

YITOAマイクロテクノロジー株式会社 プロセス技術部プロセス技術課所属 半導体プロセスエンジニア ファウンドリサービス担当

三枝 利行様

YITOAマイクロテクノロジー株式会社 営業部営業１課所属 ファウンドリサービス担当

概要

産業機器用に最適な高耐圧BCD （BIPOLAR・CMOS・DMOS）プロセスのキーデバイスとなるDMOSを、TCAD（プロセス・デバイスシミュレーション）を利用して開発した事例を紹介する。

福原 領平様

株式会社トッパン・テクニカル・デザインセンター
デバイスOEM開発部 デジタル開発チーム 係長

概要

SILVACOのIPである「AHB Performance Subsystem」を用いたセキュリティICの開発事例を紹介する。

本田 龍之介

TCADアプリケーションエンジニア

概要

近年、業界の関心を集めている新しいReRAM技術が、低消費電力、高耐久性、高速スイッチング時間のために有望な候補として浮上しています。これらのデバイスの理解を深めるために、TCADシミュレーションを用いて抵抗性スイッチングの背後にある化学プロセスを研究することができます。シルバコのデバイス・シミュレータVictory DeviceのChemistryモジュールをベースにした、包括的でありながら柔軟性のあるReRAMモデルを紹介します。

Farhad Hayat

VP of Global Marketing

Farhad Hayat is Vice President of Global Marketing chartered with defining, driving, and promoting Silvaco’s leadership in the TCAD, Custom IC and IP markets. Key areas of responsibility include strategic planning, corporate marketing, product marketing, market research, brand management, corporate communications, and ecosystem alliance programs.

Farhad joined Silvaco in January 2020 with 20+ years of experience in strategic marketing, corporate communication, product management and business development in Electronic Design Automation market. Most recently he led marketing at Synopsys for Analog/Mixed-signal simulation and Custom IC design products. Before that he held various senior marketing positions at LogicVision, Synopsys and Cadence.

Farhad holds a BSEE and MSEE from university of Tulsa, Oklahoma.

Farhad Hayat

全球市场副总裁，Silvaco

负责定义、推动和提升Silvaco在TCAD、定制IC和IP市场中的领导地位，重要责任领域包括战略规划、企业营销、产品营销、市场研究、品牌管理、企业沟通和生态系统联盟项目。 Farhad 于2020年1月加入 Silvaco，在电子设计自动化市场的战略营销、企业沟通、产品管理和业务开发方面拥有20多年的经验。此前，他领导了Synopsys的模拟/混合信号仿真和定制IC设计产品的营销工作；在LogicVision，Synopsys和 Cadence担任过多个高级营销职位。

Farhad拥有俄克拉荷马州塔尔萨大学的 BSEE 和 MSEE。

Chiping Tu

General Manager Taiwan Office

Chiping Tu is the General Manager of Silvaco Taiwan office. Since joining Silvaco in 2008, he has been in charge of sales for all Silvaco products in Taiwan and responsible of Silvaco Taiwan team management.

Chiping Tu holds a M.S in Electrical & Computer Engineering from University of Texas at Austin and a B.S. in Electrical Engineering from National Taiwan University.

Yun-Li (Charles) Li

CEO, PlayNitride Inc.

Dr. Yun-Li (Charles) Li is the CEO and co-founder of PlayNitride, one of the most advanced MicroLED companies in the world. PlayNitride was established by Dr. Li and his partners in 2014. Under Dr. Li's leadership, PlayNitride has steadily grown to more than 300 employees within 6 years and keeps the leader position in development of MicroLED display technology. From September 2019, PlayNitride starts running the first MicroLED production line in Taiwan to deliver products to customers.

Dr. Li received his Ph.D. degree from Rensselaer Polytechnic Institute (USA) with Prof. Fred Schubert in 2003. Dr. Li's Ph.D. work focused on gallium nitride (GaN) based light-emitting diodes (LEDs) and LED-based applications.

In 2020, Dr. Li received Special Recognition Award from Society for Information Display (SID). It recognized Dr. Li and his team in development and commercialization of MicroLED technology. It also indicated that MicroLED has been identified as the new generation display technology and key development topic.

Ya-Hsiang Tai

Professor, Department of Photonics, National Yang Ming Chiao Tung University

Ya-Hsiang Tai joined the faculty of National Yang Ming Chiao Tung University in 2003, where he is currently a professor in the Department of Photonics and Institute of Electro-Optical Engineering, College of Electrical and Computer Engineering. His current research emphases are in the areas of thin-film transistor (TFT) device physics, active matrix display panel and circuit design, as well as optical and X-ray imager system.

He became a member of Industrial Technology Research Institute / Electronics Research & Service Organization and the TFT LCD development department as a panel designer. He joined the project of low temperature polycrystalline silicon (LTPS) TFT development in Prime View International in 2000. In 2001, he entered Toppoly Optoelectronics Corporation, to lead the team of LTPS TFT LCD panel design.

Ya-Hsiang Tai received the B.S. and Ph.D. degrees in electronic engineering from National Yang Ming Chiao Tung University, Taiwan, in 1990 and 1996, respectively.

赵梓夷 Ziyi Zhao

高级应用工程师，Silvaco中国

复旦大学物理系硕士，曾任上海华力集成电路有限公司PDK 主任级工程师，负责PV领域rule deck开发。

WonSeok Lee

高级应用工程师，Silvaco韩国

Won-Seok Lee是Silvaco韩国的高级应用工程师。Won-Seok Lee拥有超过25年的建模和器件仿真经验，负责研究器件技术理论以及支持EDA客户的各种应用，包括CMO、显示技术和功率/RF设备等。此外，他还开发了具有高精度的AMOLED 电路模拟动态滞后模型，以仿真器件的真实特性。

Dr. Alex Samoylov

EM/IR 分析高级经理，Silvaco

Alex Samoylov在物理实现领域拥有20多年的经验，包括标准单元和晶体管级设计的电源、时序和可靠性分析等。

Yao-Wen Chang

Distinguished Professor & Dean, College of Electrical Engineering and Computer Science, National Taiwan University

Yao-Wen Chang received the B.S. degree from National Taiwan University (NTU) in 1988, and the M.S. and Ph.D. degrees from the University of Texas at Austin in 1993 and 1996, respectively, all in computer science. He is currently a Distinguished Professor and the Dean of the College of Electrical Engineering and Computer Science, NTU. His current research interests lie in electronic design automation (EDA). He has co-authored a popular 934-page EDA textbook (Morgan Kaufmann, 2009), 17 U.S. patents, and over 340 ACM/IEEE conference/journal papers, including highly cited papers on floorplanning, placement, routing, manufacturability, and FPGA design. He was ranked #1 worldwide among 40K+ researchers by the Microsoft Academy for Recent Five-Year Citations in the Hardware and Architecture Domain during 2011/2012 before the system retired. His NTUplace3 placer was transferred as the popular Custom Digital Placer of Synopsys (SpringSoft). His NTUplace4 is a 3-time champion at the DAC, ICCAD, and ISPD placement contests, then the core engine of the MaxPlace placer, a leading placer of the profit-earning Maxeda Technology, co-founded by him in 2015 and invested by leading IC design houses.

Dr. Chang received four awards at the 50th DAC in 2013, e.g., for the 1st Most Papers in DAC’s Fifth Decade (34 papers; #1 worldwide). He published the world’s most DAC+ICCAD+TCAD papers during the past three decades. He is a recipient of 11 Best Paper Awards (including the 2017 DAC Best Paper Award), the 2007 ICCAD Professor Margarida Jacome Memorial Award, an ASP-DAC Prolific Author Award in 2020, 21 top-3 place awards at ACM/IEEE EDA contests. He has received many research and teaching awards, such as the Distinguished Research Award from the Ministry of Science and Technology of Taiwan (highest honor, three times), the IBM Faculty Awards (three times), the MXIC Chair Professorship, and two distinguished (highest honor) and nine excellent teaching awards from NTU.

Dr. Chang is a fellow of the ACM and the IEEE and is currently the President of the IEEE CEDA. He has served on the editorial boards of IEEE TCAD, IEEE TVLSI, IEEE D&T, etc. He has also served as program/general/executive (steering) committee chair of ICCAD and ISPD, and ASP-DAC and FPT program chair. He is a recipient of the 2015 IEEE CEDA Outstanding Service Award and the 2012 ACM Recognition of Service Award. He has served as an independent board director of Genesys Logic, a technical consultant of Faraday, MediaTek, and RealTek, and chair of the EDA Consortium of the MOE, Taiwan.

Mike Stipe

Senior Vice President of Worldwide Sales

Mike Stipe is a sales & marketing veteran of the high-tech sector with 30 years’ experience growing companies from ground up to $1B+ in revenue. Prior to Silvaco Mike was of VP Cloud and Software sales at Zones LLC. Mike has a strong background in international markets and has worked for firms in Sweden and Australia. His previous roles include SVP Sales at Persistent Systems, SVP Worldwide Sales & Marketing at Bsquare, President and Co-founder at Arynga (acquired by Intel), VP Sales at Teleca (acquired by Harman), VP Sales at Altium, and VP Sales & Marketing at Effnet. He has also held sales leadership roles at Motorola and Wind River (acquired by Intel). Mike holds a degree in Business Administration from the College of Idaho.

Babak Taheri

CEO/CTO, Silvaco Inc

Babak Taheri is the CEO at Silvaco Inc., a leading provider of TCAD, EDA, and design IP software. He began his career at Silvaco as chief technical officer and executive vice-president of products. Previously, he was the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence.

While at IBT, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP).

Babak was the recipient of ”the perfect project award” in 2003 while at Cypress; Twice recipient of the “Diamond Chip Award” in 2013 /14 while at Freescale; recipient of the MEMS & Sensors executive of the year award in 2014, and in 2015 was the recipient of the Distinguished Engineering Alumni Medal from UC. Davis College of Engineering, where he is on the advisory board to the college.

He also held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. He received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences, has over 20 published articles and holds 28 issued patents.

Dr. Carlos Mazure

Executive Director, SOI Industry Consortium, SEMI​

Dr. Carlos Mazure is Chairman and Executive Director of the SOI Industry Consortium. Prior to SOI Industry Consortium he held executive roles at Soitec, Infineon Technologies AG and Motorola Semiconductors.

In addition to his business leadership experience, Dr. Mazure has an in-depth understanding of semiconductor technology with more than 100 patents filed worldwide and has authored over 120 scientific papers. He holds two PhDs in physics, one from the University of Grenoble, France, and the other from the Technical University of Munich, Germany.

John Kent

Executive VP, SkyWater Technology​​

John Kent is responsible for leading SkyWater’s technical vision and strategy for developing technology roadmaps, design enablement capabilities, and partnerships to facilitate successful silicon for SkyWater customers. His 40 plus years of experience in the semiconductor industry include demonstrated successes in technology development, operations, and leadership positions.,

Mr. Kent’s prior experience includes vice president of Foundry IP; Customer Design Enablement at GLOBALFOUNDRIES, executive level positions with KLA-Tencor in the Wafer Inspection Group, and technology development leadership positions at Rambus and AMIS (now ON Semiconductor). Previously, for more than two decades, he held a variety of positions at IBM Microelectronics with responsibilities for the development of various technologies, including a focus on DRAM/embedded DRAM process development.

Mr. Kent holds a Bachelor of Science degree in chemical engineering from Michigan State University. He is also the Vice Chair of the Idaho State University Foundation in Pocatello, Idaho.

Thomas Blaesi

VP & GM, EDA Division, Silvaco Inc

Thomas F. Blaesi is Vice President and General Manager of the EDA Business Unit. He is responsible for managing the development of all EDA tools including analog custom design, circuit simulation and SPICE modeling. Thomas joined Silvaco in October 2017 and held the position of Vice President of Global Marketing until December 2019. He has more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries.

Bogdan Tudor

Senior Manager, Device Characterization, Silvaco Inc

Bogdan Tudor is Head of Device Characterization for Silvaco, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software.

Jody Matos

Senior Manager Simulation, Silvaco Inc

Jody Maick Matos is a Senior Manager at Silvaco, Inc. In this position, he has been managing leading-edge R&D and business-related projects for EDA tools. His current tasks are mainly related to SPICE simulation, power, EM/IR and thermal analysis on analog, digital and mixed-signal IC designs.

Fred Sendig

Vice President of R&D, Silvaco Inc

Fred Sendig leads R&D of Silvaco’s Analog Custom Design Division. He is responsible for driving the business and development efforts for custom design, physical realization, verification, PDK development and services. He brings nearly 35 years of experience in EDA and CAD to Silvaco having previously held positions of VP CAD and Methodology at Altera, Fellow/VP of R&D at Synopsys and R&D Fellow at Cadence.

Sripriya Raghavendran

Application Engineer, Silvaco Inc

Graduated with an MSEE in analog circuits and semiconductor device physics (3.9) from San Jose State in 2000.

Last couple decades, Sripriya has been working at various semiconductor companies such as National semiconductor, Rockwell semiconductor, Sipex, Lattice semiconductor and various startups in Utah as IC product, senior product, and analog design engineer, used spice simulation tools from various industry providers. Sripriya has also worked as an Electrical Engineer with board/system design for companies in Utah and Florida and ran EMI simulations. Sripriya also has been in academia affiliated with Utah Valley University and University of Utah as Business Technology Developpement manager, managing IP for Electrical, Mechanical, and Civil engineering department. Sripriya also have enjoys teaching STEM related projects during summer for kids in Utah.

Jonathan Sanders​

Director of Product Engineering, Silvaco Inc

Jonathan Sanders leads the corporate application engineering (CAE) and process design kit (PDK) teams in the EDA division. He has held leading engineering director and managament roles at both Synopys and Cadence Design Systems since the 1990s.

Dr. Alex Samoylov

Senior Manager, EM/IR Analysis, Silvaco Inc

Alex Samoylov, has over 20 years of experience in the physical implementation area including power, timing, and reliability analysis for standard cell and transistor level designs.

Dr. Eric Guichard

VP & GM, TCAD Division, Silvaco Inc.

Dr. Eric Guichard is Vice President of Silvaco’s TCAD Division. He is responsible for managing all aspects of the TCAD division from R&D to field operations. Since joining Silvaco in 1995, he has held numerous positions including director of Silvaco France and most recently Director of Worldwide TCAD Field Operations. Prior to joining Silvaco, Guichard was a senior SOI engineer specializing in transistor and circuit aging at LETI and Thomson Military and Space.

Dr. Guichard holds an MS in material science and a Ph.D in semiconductor physics from Ecole Nationale Polytechnique de Grenoble, France.

Eric Guichard博士

TCAD业务总经理及公司副总裁，Silvaco, Inc.

Eric Guichard博士是Silvaco TCAD部门的副总裁。他负责管理TCAD部门从研发到现场实施的各个方面。自1995年加入Silvaco以来，他担任过多个职位，包括Silvaco France总监和最近的全球TCAD现场运营总监。在加入Silvaco之前，Guichard是LETI和Thomson军事和航天公司的高级SOI工程师，专门研究晶体管和电路老化。

Guichard博士拥有法国格勒诺布尔国立理工学院材料科学硕士学位和半导体物理学博士学位。

Michael Uren

Research Professor in the Centre for Device Thermography and Reliability at the University of Bristol

Michael Uren is Research Professor in the Centre for Device Thermography and Reliability at the University of Bristol, UK, and has now accumulated more than 40 years device physics experience. He did his MA and PhD in Physics at the University of Cambridge on electron transport in Si MOSFETs, followed by a postdoc at IBM, Yorktown Heights, USA. He worked at RSRE Malvern, UK (now QinetiQ) on SOI CMOS, random telegraph and 1/f noise, and interface trapping. Later he successfully implemented SiC RF power MESFET, GaN S-band and X-band MMIC processes. He moved to Bristol in 2011 to join Professor Martin Kuball’s team where he has led the device electrical research on GaN, and Ga2O3 devices. His recent interests have focused on the understanding of the role of epitaxy on device performance.

Johannes Ender

Ph.D Student

Johannes Ender finished his Master’s studies in Mechatronics at the University of Applied Sciences in Vorarlberg in 2013. After working in industry for three years he pursued the Master’s studies of Computational Science at the University of Vienna. In November 2018 he joined the Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the Institute for Microelectronics where he started his PhD studies researching the simulation of non-volatile magnetic memory devices.

François Clément

R&D Engineer, Silvaco Inc.

François J. R. Clément received the B.S. and Ph.D. degrees in electrical engineering from the Swiss Federal Institute of Technology in Lausanne (EPFL), Switzerland, in 1991 and 1995, respectively. In 1996, he was a visiting scholar with Profs. R. W. Dutton and B. A. Wooley at Stanford University.

In 1997, he joined the founders of Snaketech where he developed the first commercial solution to model cross-talk through silicon substrate ("SubstrateStorm"). After Snaketech successive acquisition by Simplex Solutions and Cadence Design Systems, the tool was renamed by “SubstrateStorm” and is now part of Cadence’s software portfolio.

In 2004, François co-founded Coupling Wave Solutions (CWS) where he serves as CTO to leverage the expertise acquired during his time at Simplex Solutions and Cadence Design Systems. His objective is to develop a comprehensive solution to address electrical signal integrity in complex integrated systems combining RF, analog and digital IPs on multi-million gate designs. Since 2020, he is helping Silvaco Advanced R&D team to push further the limits of on-chip parasitic modelling, including substrate.

François is author and co-author of several conference papers, journal articles, as well as worldwide patents.

Carlos Augusto, Ph.D.

Co-Founder and CTO, Quantum Semiconductor

Dr. Augusto is a co-founder and the Chief Technology Officer of Quantum Semiconductor. A prolific inventor, he is responsible for Quantum Semiconductor’s core technology. Dr. Augusto has been in the semiconductor industry for 20 years. Carlos has a BSc. in Physics from the Instituto Superior Técnico, Technical University of Lisbon, Portugal, M.S. in Physics of Microelectronics and Materials Science, and Ph.D. in Electrical Engineering with a specialty in device physics from the Catholic University of Leuven, Belgium. He is the author or co-author of 27 patents in image-sensors, advanced silicon devices, light-valves, optical communications, and solar cells.

Dr. Yuhao Zhang

Assistant Professor, Center for Power Electronics Systems, Virginia Tech

Dr. Yuhao Zhang is an assistant professor with the Center for Power Electronics Systems (CPES) at Virginia Tech. Before joining CPES, he worked as a postdoctoral associate at Massachusetts Institute of Technology (MIT) from 2017 to 2018. He received his Ph. D. and S. M., both in electrical engineering from MIT in 2017 and 2013, respectively. Prior to joining MIT, he received his B. S. in physics from Peking University in 2011 with the highest honor. He received the MIT Microsystems Technology Laboratories Doctoral Dissertation Award in Spring 2017 and the IEEE George Smith Award in 2019. His research interest is at the intersection of power electronics, micro/nano-electronic devices, and advanced semiconductor materials.

Dr. Viktor Sverdlov

Director, Institute for Microelectronics, TU Wien

Viktor Sverdlov is currently heading the Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the Institute for Microelectronics, TU Wien, Austria. His research interests include device simulations, computational physics, solid-state physics, spintronics and nanoelectronics. Viktor holds his Master’s and PhD degrees in Theoretical Physics from the State University of Leningrad/St.Petersburg, and his Habilitation in Microelectronics from TU Wien. Viktor worked as a staff research scientist at the V.A.Fock Institute of Physics, State University of St.Petersburg, Université de Genève, University of Oulu, Helsinki (Aalto) University of Technology, Freie Universtät Berlin, and State University of New York at Stony Brook before he joined the Institute for Microelectronics, Technische Universität Wien, in 2004.

Wolfgang Goes

Sr. Development Engineer, Silvaco Inc.

Dr. Wolfgang Goes is a development engineer in Silvaco’s TCAD Division. Since joining Silvaco in 2016, he has worked primarily on Victory Device but also on Atlas and is responsible for reliability issues and memory technologies. Dr. Goes holds an MSc in Technical Physics and a PhD in Electrical Engineering, both from the TU Vienna. He continued working there as a post-doc at the Institute for Microelectronics focusing on reliability issues in microelectronic devices.

Dr. Tillmann Kubis

Katherine Ngai Pesic & Silvaco Research Assistant Professor of Electrical and Computer Engineering

Prof. Dr. Tillmann Kubis is leader of Purdue’s NEMO5 development team. His research interest includes all topics of equilibrium and non-equilibrium phenomena in nanodevices and molecules. This covers electronic and phonon bandstructures as well as heat, charge and spin transport in nanodevices. Dr. Kubis holds a Dr. rer. nat. in theoretical semiconductor physics from the Technische Universität München, Garching, Germany.

Alexander Toifl

Doctoral student in process TCAD, Institute for Microelectronics, TU Wien

Alexander Toifl is currently pursuing a doctoral degree in the area of process TCAD with the Christian Doppler Laboratory for High Performance at the Institute for Microelectronics, TU Wien, Austria. His research interests include anisotropic etching and epitaxy of nonplanar three-dimensional topographies and post-implantation annealing of SiC and GaN. Alexander Toifl holds a Bachelor's degree in Electrical Engineering and a Master's degree in Microelectronics and Photonics from TU Wien.

Richard Trihy

Vice President of Engineering, Design Enablement, GLOBALFOUNDRIES

Richard Trihy is Vice President Design Enablement at GLOBALFOUNDRIES where he is responsible for the delivery of EDA enablement (including Process Design Kits, Compact Models and Design Methodology) for all Semiconductor design platforms at GLOBALFOUNDRIES. Richard joined GLOBALFOUNDRIES in 2009. Prior to GLOBALFOUNDRIES Richard held R&D leadership roles in EDA at Synopsys and Cadence. Richard received his B.E. and M.Eng.Sc degrees in Electrical Engineering from University College Cork, Ireland and his Ph.D in Electrical and Computer Engineering from Carnegie Mellon University Pittsburgh PA.

Gurtej Sandhu

Senior Fellow and Vice President, Micron Technology

Gurtej Sandhu is Senior Fellow and Vice President at Micron Technology. In his current role, he is responsible for Micron’s end-to-end (Si-to-Package) R&D technology roadmaps. The scope includes driving cross-functional alignment across various departments and business units to proactively identify technology gaps, and managing the engineering organization to resource and execute on developing innovative technology solutions for future memory scaling. Dr. Sandhu’s responsibilities include leading several internal project teams worldwide and managing interactions with research consortia around the world. Dr. Sandhu received a degree in electrical engineering at the Indian Institute of Technology, New Delhi, and a Ph.D. in physics at the University of North Carolina, Chapel Hill, in 1990. He holds over 1,300 U.S. patents and is recognized as one of the top inventors in the world. Dr. Sandhu is a Fellow of IEEE. In 2018, he received the IEEE Andrew S. Grove Award for outstanding contributions to silicon CMOS process technology that enables DRAM and NAND memory chip scaling.

Rahul Goyal

Vice President and Director of R&D Strategic Enablement, Intel

Goyal has global responsibility at Intel for strategic sourcing, supply chain strategy, strategic collaborations, ecosystem enablement, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development. Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science in Pilani, India, and a master’s degree in computer engineering from Syracuse University in New York.

Jonghoon Shin

Principal Engineer, Samsung Foundry

Jonghoon Shin is a Principal Engineer at Samsung Foundry and responsible for Security IP design in IP development team. He is engaged in the development of security and crypto hardware for various products such as mobile, automotive, IoT and smart card. His research interests include SoC security architecture, crypto algorithm acceleration, public key cryptosystem application, and secure implementation against side channel attack.

Jonghoon Shin received his B.S, M.S. and Ph.D. degrees in electrical engineering from POSTECH, Pohang, Korea.

Ken Li

Vice-President, Rafael Microelectronics Inc.

Following Ken’s first career at Altera (USA) in 1988 as circuit designer. , Ken worked for National Semiconductor(USA) and S3 Graphics (USA), responsible for Video/Graphic related mixed signal blocks design and COT management. In 2005, Ken co-founded Tenor Electronics (Taiwan/Beijing/USA) with focus on mobile audio codec and DAB IC developments. Tenor was acquired by AIT (Alpha-Imaging Technology, Taiwan) in 2007. Ken devoted himself on high performance audio codec, MIPI, HDMI and USB interface IP during 5 years of stay at AIT. In 2011, Ken founded Analog Chip Corp. (Beijing) with IP and SOC design service business. Ken left Analog Chip in 2015 and Joined Brite semiconductor (Shanghai) as Vice President of IP development. In 2017, Ken joined Rafael Microelectronics as Vice President to head IOT wireless Business Unit.

Ken received his BSEE from National Chiao-Tung University in 1984 and MSEE from Portland State University in 1988.

Cashew Chen

Vice-President, Rafael Microelectronics Inc.

Cashew joined Accton (Taiwan), a leading data center and enterprise switch company, in 1988 and worked in Accton for 20 years as Corporate VP before he joined Ralink, a WiFi/BT IC design company, in 2008 as VP of System Design. Cashew joined Mediatek Wireless Connectivity BU (WCN) following MTK’s acquisition of Ralink in 2010, dedicated to WiFi/BT system design and customer applications. He also work for Nephos, a Mediatek Subsidiary designing 6.4T switch silicon as Business Development VP before he joined Vertexcom as Marketing VP promoting PLC/Sub-Ghz dual-mesh based multi-protocol IOT applications in 2017. In 2019 Cashew Joined Rafael Micro as VP and head of Optical Communication BU.

Cashew received his BSEE from National Cheng-Kung University (Taiwan) in 1986 and MSEE from University of Maryland (USA) in 1992. He also received EMBA from National Cheng-Kung University (Taiwan) in 2001.

Sharmistha Sinha

Senior Design Engineer, ST Microelectronics

Sharmistha Sinha is a Senior Design Engineer at ST Microelectronics. She has 5 years of experience in Standard Cell domain in Semiconductor industry. She is working with STM from almost past 3 years. She has worked with NXP and Maxim before joining STM. She has a master’s degree in VLSI from Amity University, Noida.

Jeff Elias

VP & GM, IP Division, Silvaco, Inc.

Jeff Elias is responsible for managing all semiconductor design IP business at Silvaco including relationships with foundries and other IP partners. He joined Silvaco in June 2017 as a business advisor before taking on his current role in December 2019. He has more than 20 years of global experience in semiconductors, systems, and software as a sales and marketing executive, with positions at Transpacific IP Group, Spin Transfer Technologies, FSA Technologies, SIVRAL, Foveon, and MOSAID.

Jeff holds a BSEE from the University of Michigan and an MBA from the Leavy School of Business, Santa Clara University.

仲島 義晴様

株式会社ジャパンディスプレイ 執行役員 CTO 兼 R&D本部長

1990年　ソニー株式会社入社
1995年-96年　マサチューセッツ工科大学客員研究員
2012年　株式会社ジャパンディスプレイに移籍
2019年　同社執行役員CTO 兼R&D本部長

吉崎 昇一様

シリコンライブラリ株式会社 取締役

1986年　松下電器産業（現パナソニック）入社
2005年　シリコンライブラリ入社
2010年　同社　取締役　HDMI, DisplayPortなどのインタフェース用IP開発を推進

右田 学様

協栄産業株式会社 R&D事業部/IC開発第二部/部長

1995年　協栄産業株式会社入社
1995年　大手半導体メーカーの開発専属としてICアナログレイアウト設計を担当
2004年　USAにて現地エンジニアと高速I/F開発に従事
2005年　シルバコツールを適用し事業拡大へ向け、様々な半導体メーカーのIC開発をスタート
2010年　自社初となるT/K案件のレイアウトプロジェクトリーダーとして開発を担当
2017年　マレーシアにて大手メーカー現地エンジニアへアナログレイアウトを講義

分島 彰男様

名古屋工業大学 准教授

1994年～2010年　日本電気（株）にて、無線通信用化合物半導体(GaAs, InP, GaN)トランジスタの研究開発に従事
2010年～　現職にて、GaNトランジスタの研究ならびにその無線通信や無線電力伝送応用にむけた検討までを研究対象としている

北村 元樹様

YITOAマイクロテクノロジー株式会社 プロセス技術部プロセス技術課所属 半導体プロセスエンジニア ファウンドリサービス担当

入社以来、プロセスエンジニアとして半導体プロセス開発に従事。
現在は、半導体プロセス担当としてファウンドリサービスの拡販を担当。

三枝 利行様

YITOAマイクロテクノロジー株式会社 営業部営業１課所属 ファウンドリサービス担当

前工程のライン管理及び工程改善に従事。5S活動の推進も手掛ける。
現在は、営業担当としてファウンドリサービスの拡販を担当。

福原 領平様

株式会社トッパン・テクニカル・デザインセンター
デバイスOEM開発部 デジタル開発チーム 係長

2003年4月 （株）トッパン・テクニカル・デザインセンター入社
入社以来、フロントエンドエンジニアとしてフラッシュメモリやCMOSイメージセンサーなどの設計開発に従事。2020年4月からは現在の部署であるOEM開発部に配属となり、OEM製品の企画・提案を担当している。

津村 明宏 様

株式会社産業タイムズ社 電子デバイス産業新聞 編集部 編集長

1995年3月 関西大学 経済学部卒。1999年3月 株式会社産業タイムズ社に入社。電子デバイス業界の専門紙である電子デバイス産業新聞（旧・半導体産業新聞）の記者として、2007年より副編集長、2009年12月より編集長。

Anand Kumar Mishra

Senior Manager, ST Microelectronics

Anand Kumar Mishra graduated from Institute of technology Banaras Hindu University (now IIT-BHU) in 2001. He worked for SRAM development in ST for 16 years before joining standard cell development team. His topics of interest are high density SRAM, standard cell for low power applications and process monitoring structures.

He is currently serving as senior Manager in Standard cell development team at ST Microelectronics PVT Ltd Noida.

Firas Mohamed

VP Advanced R&D & GM Silvaco France

Dr. Firas Mohamed will give his perspective on the means to achieve practical simulation and Monte Carlo analysis of full-chip analog and memory designs.

Simon-Alexis Abric

Corporate Application Engineer

Mr. Simon-Alexis Abric is a Corporate Application Engineer for Silvaco France. He is responsible for customer technical support for reduction (Jivaro) and parasitic analysis (Alps) products. Mr. Abric earned a Master of Engineering degree in integrated circuits and systems in 2013 from the engineering school ENSEIRB in Bordeaux, France.

Jean-Baptiste Duluc

Senior Corporate Application Engineer

Dr. Jean Baptiste Duluc is the core-competency application engineer in charge of VarMan product development at Silvaco. He joined Silvaco in 1999 as support engineer for the characterization and modeling software Utmost. Dr. Duluc holds a MS and PhD in microelectronics from the University of Bordeaux, France.

Kavya Prabha Divakarla

Automotive Systems Functional Safety Architect, NXP Semiconductors

Dr. Divakarla has been with NXP since 2017 working within the Microcontroller and Microprocessor business line in the Automotive Business Unit. In her current role as the Functional Safety Architect/ Manager, she is focused on the Functional Safety for Autonomous, Vision and Gateway products. She received her B.Tech. degree in Process Automation Technology in 2012 and M.A.Sc. and Ph.D. in Electrical and Computer Engineering in 2014 and 2018 respectively from McMaster University, Canada.

Johan Van Ginderdeuren

Director, IP Blocks Licensing, NXP Semiconductors

Mr. Van Ginderdeuren will present on NXP's ultra-low power CoolFLux DSP for digital audio, software defined radio, wireline processing, and intelligent sensor processing applications.

Jin Jang

Director of the Advanced Display Research Center

Jin Jang is a Professor at Department of Information Display of Kyung Hee University. His current research programs are in oxide and LTPS TFTs for displays, TFT circuits and TFT application to sensors, QLED, Micro-LED and flexible AMOLED. He is the author or co-author of over 1,000 technical publications of which over 600 are in SCI Journals such as Nature, Advanced Materials, Advanced Functional Materials, Energy Environmental Science, APL, IEEE TED and IEEE EDL. He is currently a Director of Advanced Display Research Center (ADRC) and had served as Program Chair of SID Symposium 2007 and General Chair of SID Display Week in 2009 and General Chair of IMID 2012, 2013. He is a Fellow of SID and he was awarded George Smith Award from IEEE in 2012, Slotto Owaki Prize from SID in 2015 and Ho-Am Award in 2017.

Jeong-Ik Lee

Assistant Vice President Reality Devices Research Division

Jeong-Ik Lee received his B.S., M.S., and Ph.D. Chemistry degrees from Korea Advanced Institute of Science and Technology (KAIST) in Daejeon, South Korea in 1992, 1994, and 1997, respectively. After graduating, he joined IBM Almaden Research Center in San Jose, CA, USA as a postdoctoral associate, and worked on OLED materials. He joined ETRI in 1999 and continued his research on OLED materials and devices. He has led the Reality Devices Research Division of ETRI since 2017 and has worked on the convergence of display and sensor technologies.

Carlos Mazure博士

执行董事，SOI Industry Consortium, SEMI​

Carlos Mazure博士是SOI Industry Consortium的董事会主席和执行董事。在这之前，他曾在 Soitec、英飞凌和摩托罗拉半导体公司担任管理职务。

Carlos Mazure博士不仅有丰富的商业领导经验，他还对半导体技术有深入的了解，在全球申请了 100 多项专利并撰写了 120 多篇科学论文。他拥有两个物理学博士学位，一个来自法国格勒诺布尔大学，另一个来自德国慕尼黑技术大学。

John Kent

副总裁，SkyWater Technology​​

John Kent 负责 SkyWater 的技术愿景和战略，推动公司技术路线图、设计启用能力和合作伙伴关系等，帮助 SkyWater 的客户成功制造芯片。他在半导体行业拥有四十多年的经验，在技术开发、运营和管理岗位上都有成功的经验。

John Kent 曾任 Foundry IP副总裁、GLOBALFOUNDRIES 的客户设计支持、Wafer Inspection Group 旗下 KLA-Tencor 的管理层，Rambus 和 AMIS 的技术开发负责人（现为ON Semiconductor）等。更早的二十多年，他在 IBM 微电子公司担任过各种职位，负责多个技术的发展，包括 DRAM/嵌入式 DRAM 的流程开发。

John Kent 拥有密歇根州立大学化学工程理学学士学位，是爱达荷州波卡泰洛爱达荷州立大学基金会的副主席。

Sripriya Raghavendran

应用工程师，Silvaco, Inc.

Sripriya于2000年毕业于圣何塞州立大学，获得模拟电路和半导体器件物理方向的MSEE学位。

在过去的几十年里，Sripriya在多家半导体公司工作，如National semiconductor, Rockwell semiconductor, Sipex和Lattice semiconductor等，任职IC产品高级工程师、模拟设计工程师和电路板/系统设计电气工程师等，有丰富的SPICE模拟工具应用经验，熟悉EMI模拟。

Sripriya也很喜欢在夏季为犹他州的孩子们教授STEM相关项目。

Sharon Fang

VP & GM, Silvaco China

Sharon Fang is a seasoned executive with a distinctive combination of sales, marketing, strategic thinking and operational skills, successful track record and driving revenue growth as both an individual contributor and sales manager in EDA. Sharon currently serves as General Manager for Silvaco China. In her role as head of China region, Sharon is putting together the necessary processes and infrastructure to streamline the sales process, empowering individuals and teams to maximize value to customer as well as ROI. The China organization is focused on helping drive customer success through the use of Silvaco TCAD-to-sign off solutions, modeling services, IP management & compliance software while driving business growth for the company.

Sharon holds a bachelor of Art degree from Southwest China Normal University and an MBA degree from Saint Mary’s College of California.

Dan Jiang

Application Engineer, Silvaco China, Ltd

Dan Jiang is responsible for the EDA tools supporting in Silvaco China. He has more than 10 years of experience in design， EDA tools validation and project CAD. She received her B.E. from SiChuan university.

李栋良 Dongliang Li

资深TCAD工程师，Silvaco中国

拥有有多年半导体器件仿真建模经验，帮助客户实现工艺结构和器件特性方面的需求。毕业于东南大学。

赵友来 Ellison Zhao

副总经理，Silvaco中国

复旦大学硕士，在EDA软件及芯片IP核领域拥有超过20年行业经验。

Kevin Chang

TCAD Application Engineer Manager, Silvaco China Co. Ltd

Kevin Chang is a TCAD application engineer manager in Silvaco China, has worked in the TCAD area of the semiconductor and display market for more than 10 years, and has lots of experience supporting customer success in process and device simulation and 3D physical parasitic extraction tools.

常志强 Kevin Chang

TCAD 技术支持部经理，Silvaco中国

长期从事 Silvaco TCAD 在国内的技术推广、客户支持等工作，致力于 TCAD 在半导体工艺和器件中的仿真应用，帮助客户建立 TCAD 仿真能力和平台。本科毕业于南京大学，硕士毕业于复旦大学.

Ke Liu

Application Engineer Manager, Silvaco China, Ltd

Ke Liu is responsible for the EDA tools supporting in Silvaco China. He has more than 10 years of experience in simulation division. He received his M.S Microelectronics from NUDT.

Takeshi Kuwagagi

APAC FAE manager, Silvaco Japan

Takeshi Kuwagaki received the B.S. degree from applied physics engineering from Osaka City University, Osaka, Japan, in 1994. He joined Silvaco Japan Co,. Ltd., Yokohama, Japan, in 1997 as an application engineer to be engaged in customer and software development supports of layout design, design verification, and parasitic extraction tools. Now he is Engineering Manager in SILVACO Japan, and APAC FAE manager.

Alex Grudanov

Senior Director Advanced R&D

Former CEO and co-founder of POLYTEDA CLOUD LLC. Cloud SaaS EDA pioneer, first CEO of Ukrainian SME who won H2020 Phase2 grant funding from European Commission.

Scott Wedge

Senior R&D Engineer

Scott spent his first decade in electronics as an AMS/RFIC design engineer for mobile, airborne, and satellite communications systems. His interests in developing better simulation & modeling solutions led him into the electronic design automation industry where he has made numerous contributions to many successful simulation tools at Keysight, Mentor, and Synopsys. Scott served as Principal Investigator on several DARPA funded projects aimed at advancing high-speed high-frequency mixed-domain simulation and design techniques. His current work with the Silvaco R&D team is to further enhance the RF and signal integrity analysis capabilities of SmartSpice and SmartSpice RF. Scott received his Ph.D. from the California Institute of Technology.

Vincent Annezo

Corporate Application Engineer

Vincent is a Corporate Application Engineer dedicated to VarMan improvement and support. Prior to Silvaco, he worked as a Software Validation and Application Engineer at Aselta (French EDA start up) for 9 years.

Mike Uren

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Jean Pierre Raskin

Professor at Université catholique de Louvain

Jean-Pierre Raskin received the M.S. and Ph.D. degrees in applied sciences from Université catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium, in 1994 and 1997, respectively. He has been a Full Professor at the Electrical Engineering Department of UCLouvain since 2000. His research interests are the modeling, wideband characterization and fabrication of advanced SOI MOSFETs as well as micro and nanofabrication of MEMS / NEMS sensors and actuators, including the extraction of intrinsic material properties at nanometer scale. He has been IEEE Fellow since 2014. He was the recipient of the Médaille BLONDEL 2015, the SOI Consortium Award 2016, the European SEMI Award 2017, the Médaille AMPERE 2019, and the Georges Vanderlinden Prize 2020, in recognition in his vision and pioneering work for RF SOI. He is author or co-author of more than 350 scientific journal articles. In 2017, he received with the NGO Louvain Cooperation the European Global Education Innovation Award for the lecture-project IngénieuxSud.

Dr. Munaf Rahimo

Founder and General Manager - mqSemi AG, Siwtzerland

Dr. Munaf Rahimo has been involved in the research and development of power semiconductor devices for nearly 30 years with approximately 25 years working in industry. He has contributed to the development of a wide range of power semiconductor device technology and product platforms such as IGBTs, Diode, Thyristors and SiC MOSFETs. Since 2000, he held many technical positions at ABB Switzerland Ltd. and was awarded with the prestigious title of ABB Corporate Executive Engineer in 2012. He left ABB in 2018 to explore consulting and entrepreneurial business models where he founded mqSemi AG in 2019 as a power semiconductor start-up company.

Stefania Carapezzi

Post Doc - Centre National de la Recherche Scientifique

Dr. Stefania Carapezzi is currently holding the position of Post-Doc Researcher at the group PHYDENANO (https://www.lirmm.fr/aida-todri-sanial/) of Dr. Aida Todri-Sanial, Microelectronics Department, LIRMM, University of Montpellier, CNRS, Montpellier, France. Her research focuses in the field of Technology Computer Aided Design (TCAD) modeling and simulation of semiconductor devices. Presently, she is investigating Beyond CMOS devices: 1) vanadium-dioxide oscillators and 2) 2D Molybdenum disulfide memristors, to be applied in Oscillatory Neural Networks, an innovative neuromorphic computing architecture which is at the core of the H2020 European Project NeurONN (https://www.neuronn.eu/). Previously, she was involved in developing TCAD models for nanoscaled transistors, such as short channel double-gate III-V MOSFETs, and suspended carbon nanotube FET. Carapezzi received her Ph. D. in Physics at the University of Bologna, Bologna, Italy. Prior to joining CNRS she was Research Fellow at the Department of Physics and then at the Advanced Research Center on Electronic System, University of Bologna.

Johannes Ender

Ph.D Student

Johannes Ender finished his Master’s studies in Mechatronics at the University of Applied Sciences in Vorarlberg in 2013. After working in industry for three years he pursued the Master’s studies of Computational Science at the University of Vienna. In November 2018 he joined the Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the Institute for Microelectronics where he started his PhD studies researching the simulation of non-volatile magnetic memory devices.

Michael Simmons

Technical Fellow, Wireless, Microchip Technology Inc.

Michael Simmons is a Technical Fellow and Manager of the Wireless Systems and SoC Architecture group at Microchip Technology Inc. His 20+ year career has spanned Process Engineering, Design/Verification and Systems Engineering/SoC Architecture, previously at Freescale (NXP), and currently at Microchip Technology. He holds multiple patents in the areas of Networking, Security and Low Power.

Alex de la Bastie

Business Development Director, AP Memory

Alex de la Bastie is in charge of Business Development at APMemory, dealing with EMEA and US customers and partners. He is over 20 years of experience in the semiconductor industry include a specific focus on low power memory, sales team leadership and business development. Alex de la Bastie ‘s prior experience includes Sales Director at Micron, Managing Director at Elpida Memory Europe, and a variety of Sales & marketing positions at Elpida and NEC Electronics. Alex de la Bastie holds an Electronics Engineering degree from ESIEE Paris university and a MBA from emlyon business school.

Osvaldo Martinello

Senior R&D Director for the Foundation IP Group, Silvaco, Inc.

Osvaldo Martinello is the Sr. R&D Director for the Foundation IP group at Silvaco, in Santa Clara, California, where he leads the development of tools for IP design and optimization. He holds a Computer Engineering degree and a Computer Science MSc, both received from UFRGS, in Porto Alegre, Brazil.

Francois Clement

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Stefano Pettazzi

Senior Applications Engineer

Stefano Pettazzi received his M.S. degree in Electrical and Electronics Engineering from University of Pavia, Italy. He has more than 20 years of experience in EDA and microelectronics companies. Since 2012 he has been working at Silvaco as Senior Applications Engineer supporting EDA software for both Back-End and Front-End design flows.

Alex de la Bastie

商务总监，爱普科技, AP Memory

Alex de la Bastie负责AP Memory的商务，与EMEA和美国的客户和合作伙伴保持密切联系。Alex de la Bastie在半导体行业有超过20年的经验，包括低功耗内存开发、管理销售团队和推动业务发展。曾任职Micron公司销售总监、Elpida Memory Europe公司董事总经理，以及Elpida和NEC Electronics的多个销售和市场营销职位。Alex de la Bastie有ESIEE Paris大学的EE学位和Emlyon商学院的MBA学位。

Alex de la Bastie

商务总监，爱普科技, AP Memory

Alex de la Bastie负责AP Memory的商务，与EMEA和美国的客户和合作伙伴保持密切联系。Alex de la Bastie在半导体行业有超过20年的经验，包括低功耗内存开发、管理销售团队和推动业务发展。曾任职Micron公司销售总监、Elpida Memory Europe公司董事总经理，以及Elpida和NEC Electronics的多个销售和市场营销职位。Alex de la Bastie有ESIEE Paris大学的EE学位和Emlyon商学院的MBA学位。

Osvaldo Martinello

Foundation IP 业务高级研发总监，Silvaco, Inc.

Osvaldo Martinello是 Silvaco Foundation IP团队的高级研发总监，领导 IP 设计和优化工具的开发。他拥有巴西UFRGS的计算机工程学位和计算机科学硕士学位。

石立丽 Lili Shi

EDA高级应用工程师，Silvaco中国

毕业于电子科技大学微电子与固体电子专业硕士，曾担任高速电路设计资深工程师，有近10年的电路设计经验。

Bogdan Tudor

高级经理, Silvaco Inc

Silvaco器件特征化负责人，领导着Utmost和Modeling Service团队。Bogdan Tudor在模型开发和特征化软件方面拥有超过 20 年的经验。

刘客 Ke Liu

技术支持经理，Silvaco中国

负责Silvaco中国的EDA 软件和Foundation IP的技术支持工作。硕士毕业于国防科技大学，在电路仿真、标准单元库设计和SRAM等领域有十多年的工作经验。

Dr. Munaf Rahimo

创始人兼总经理 ，mqSemi AG，Siwtzerland

Munaf Rahimo 博士从事功率半导体器件研发工作近30年，在工业界工作近25年，曾参与多项功率半导体器件和产品平台（如 IGBT、二极管、晶闸管和 SiC MOSFET）的开发。自 2000年起，他在 ABB 瑞士担任多个技术职位，于2012年被授予著名的 ABB 企业执行工程师称号； 2018 年，离开 ABB，进入咨询领域；2019 年，创立功率半导体公司mqSemi AG。

Jeff Elias

IP业务总经理及公司副总裁，Silvaco, Inc.

Jeff Elias负责管理Silvaco的所有半导体设计IP业务，包括与晶圆厂和其他IP合作伙伴的关系。他于2017年6月加入Silvaco，担任业务顾问，并于2019年12月担任目前的职位。他在半导体、系统和软件领域拥有超过20年的全球经验，曾在 Transpacific IP Group, Spin Transfer Technologies, FSA Technologies, SIVRAL, Foveon和 MOSAID等担任销售或市场营销负责人。

Jeff 拥有密歇根大学的电子工程学士学位和圣克拉拉大学利维商学院的 MBA 学位。

赵梓夷 Ziyi Zhao

高级应用工程师，Silvaco中国

复旦大学物理系硕士，曾任上海华力集成电路有限公司PDK 主任级工程师，负责PV领域rule deck开发。

Jean Pierre Raskin

鲁汶大学教授

拥有比利时UCLouvain应用科学硕士与博士学位。从 2000 年起，Jean-Pierre Raskin进入UCLouvain 大学电气工程系担任教授，研究领域为SOI MOSFET 建模、材料的宽带表征和制造，以及 MEMS/NEMS 传感器的微纳米制备（包括在纳米尺度上提取本征材料特性)。Jean-Pierre Raskin著有 350 多篇科学期刊文章，自 2014 年起成为IEEE 成员。因为在SOI射频领域的远见卓识和开创性工作，Jean-Pierre Raskin获得了多项表彰，例如2015 年的金色奖章，2016 年的SOI联盟奖，2017 年的欧洲 SEMI 奖，2019 年的安培奖，2020 年的乔治·范德林登奖，其与非政府组织 Louvain Cooperation合作的项目还获得了2017年的欧洲全球教育创新奖。